1. Field of the Invention
The invention relates to a memory apparatus and to a method for reading data from memory cells in a memory apparatus.
2. Description of the Related Art
Two fundamental parameters of memory apparatuses, particularly modern DRAM memory apparatuses, are the “word line cycle time” (row cycle time) tRC and the “read latency” tRL. The word line cycle time tRC is the minimum period of time which elapses between opening word lines in the same memory bank. The read latency tRL denotes the time delay between a read command RD and valid data at the data output of the memory apparatus.
The maximum bandwidth which can be attained for random access to memory cells in a memory cell array in a memory apparatus is ultimately limited by the word line cycle time tRC. Thus, from the input of a read command up to the output of valid data at the data output of the memory apparatus, a maximum period of time known as the “effective” read latency tRL(eff) elapses in practice. This effective read latency tRL(eff) is the maximum period of time which is required to terminate the preceding word line cycle (i.e., tRC) and the “intrinsic” read latency tRL, as expressed in the following equation:tRL(eff)=tRC+tRL
To attain the smallest possible effective read latency tRL(eff), a short word line cycle time tRC thus needs to be made possible, which means that tRC is a fundamental parameter for fast memory apparatuses.
Although other fundamental parameters of modern semiconductor memory apparatuses, particularly their power consumption, the maximum clock frequency, the scale of integration, etc., have been constantly improved with each new semiconductor memory generation in recent time, the reduction in the word line cycle time tRC, which is desirable from the above viewpoints, has been comparatively small in past years.
The physical parameters determining the word line cycle time tRC are essentially parasitic capacitances and line resistances. It has been found that these physical parameters are improved only to an insignificant extent with the progress in modern semiconductor technology, if any improvement can be seen at all. In addition, increases in the size of the cell arrays generally result in an increase in parasitic influences, which have a disadvantageous effect on tRC if disadvantageously great use of silicon area is not accepted.
To simplify understanding of the invention which will be explained later, the text below describes the timing of a typical word line cycle (row cycle) in a conventional DRAM store. Although the exemplary description is directed at a DRAM store in this case, similar designs are often also implemented for other memory architectures, such as SRAMs.
A typical minimum word line cycle (row cycle) in a DRAM store having a multiplicity of memory cells, where each of the memory cells has an associated word line and an associated bit line, comprises the following three sequences:
1. A Word Line Opening and Data Reading Step (BLSENS)
In this step, the word line in question is “opened”, i.e., the cell transistors for the memory cells which are connected to the word line are put into an electrically conductive state. The storage capacitors for the memory cells are thus conductively connected to their respective associated bit lines, which means that the data stored in the memory cells can be read in a known manner. The time tBLSENS required for opening the word line and for reading the data stored in the memory cells is thus determined preliminarily by that time which is needed to open the word line, to develop the bit line signal and to read the data to a register.
2. A Writing or Charging Step (CHARGE)
When a word line is open, new data can be written to the desired memory cell capacitor by applying a suitable voltage to the respective bit line using a write command. If a write command is not involved but rather a read command, then the data previously read in step 1 (BLSENS) are written back to the memory cell capacitor in the same way to bring its voltage signal back to the prescribed nominal value. In a similar manner, a refresh command also involves the data previously read in step 1 being written back to the memory cell capacitor. The delay tCHARGE which results from this charging step is thus determined essentially by the available charging current and also by the capacitance of the memory cell capacitor for the DRAM memory cells.
3. An Electrical “Biasing Step” or Erasure Step for the Bit Lines (Precharge, BLPRE)
Since, following execution of the charging step (CHARGE), as described above under step 2, the bit lines are either at the predetermined lower voltage potential or at the predetermined upper voltage potential, the bit lines first need to be brought to a suitable predetermined voltage potential to prepare the bit lines for a fresh opening and reading step (BLSENS), i.e., the bit lines need to be electrically “biased” to a suitable voltage potential, which is also called “erasing” the bit lines. Erasing the bit lines has an associated time delay tBLPRE.
The three time delays tBLSENS, tCHARGE and tBLPRE cited above result altogether in the (minimum) word line cycle time tRC (row cycle time). Between write, read and refresh commands, there is no difference in terms of the minimum word line cycle time tRC required.